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SAA7111A

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Datasheet

SAA7111A
(Product Specification)
15-May-98, 72 pages, 337 kB

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Enhanced Video Input Processor (EVIP)

General description
Features
Products/packages
Chemical content
Pricing/ordering/availability
Samples
Applications
Block diagrams/pinning
Design support
Parametrics/similar products
Print/email

General description

The Enhanced Video Input Processor (EVIP) is a combination of a two-channel analog preprocessing circuit including source selectionanti-aliasing filter and ADCan automatic clamp and gain controla Clock Generation Circuit (CGC)a digital multi-standard decoder (PAL BGHIPAL MPAL NNTSC M NTSC-Japan NTSC N and SECAM)a brightness/contrast/saturation control circuita colour space matrix (see Fig.1) and a 27 MHz VBI-data bypass.

The pure 3.3 V CMOS circuit SAA7111Aanalog front-end and digital video decoderis a highly integrated circuit for desktop video applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PALSECAM and NTSC signals into CCIR-601 compatible colour component values. The SAA7111A accepts as analog inputs CVBS or S-video (Y/C) from TV or VTR sources. The circuit is I2C-bus controlled. The SAA7111A then supports several text features as Line 21 data slicing and a high-speed VBI data bypass for Intercast.

Features

  • Four analog inputs, internal analog source selectors, e.g. 4 ' CVBS or 2 ' Y/C or (1 ' Y/C and 2 ' CVBS)
  • Two analog preprocessing channels
  • Fully programmable static gain for the main channels or automatic gain control for the selected CVBS or Y/C channel
  • Switchable white peak control
  • Two built-in analog anti-aliasing filters
  • Two 8-bit video CMOS analog-to-digital converters
  • On-chip clock generator
  • Line-locked system clock frequencies
  • Digital PLL for horizontal-sync processing and clock generation
  • Requires only one crystal (24.576 MHz) for all standards
  • Horizontal and vertical sync detection
  • Automatic detection of 50 and 60 Hz field frequency, and automatic switching between PAL and NTSC standards
  • Luminance and chrominance signal processing for PAL BGHI, PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43, NTSC-Japan and SECAM
  • User programmable luminance peaking or aperture correction
  • Cross-colour reduction for NTSC by chrominance comb filtering
  • PAL delay line for correcting PAL phase errors
  • Real time status information output (RTCO)
  • Brightness Contrast Saturation (BCS) control on-chip
  • The YUV (CCIR-601) bus supports a data rate of:
    ? 864 ' fH= 13.5 MHz for 625 line sources
    ? 858 ' fH = 13.5 MHz for 525 line sources.
  • Data output streams for 16, 12 or 8-bit width with the following formats:
    ? YUV 4 :1 :1 (12-bit)
    ? YUV 4 :2 :2 (16-bit)
    ? YUV 4 :2 :2 (CCIR-656) (8-bit)
    ? RGB (5, 6and 5) (16-bit) with dither
    ? RGB (8, 8and 8) (24-bit) with special application.
  • Odd/even field identification by a non interlace CVBS input signal
  • Fix level for RGB output format during horizontal blanking
  • 720 active samples per line on the YUV bus
  • One user programmable general purpose switch on an output pin
  • Built-in line-21 text slicer
  • A 27 MHz Vertical Blanking Interval (VBI) data bypass programmable by I2PC-bus for INTERCAST applications
  • Power-on control
  • Two via I2PC-bus switchable outputs for the digitized CVBS or Y/C input signals AD1 (7 to 0) and AD2 (7 to 0)
  • Chip enable function (reset for the clock generator and power save mode up from chip version 3)
  • Compatible with memory-based features (line-locked clock)
  • Boundary scan test circuit complies with the ?IEEE Std. 1149.1- 1990? (ID-Code = 0 F111 02 B)
  • I2PC-bus controlled (full read-back ability by an external controller)
  • Low power (<0.5 W), low voltage (3.3 V), small package (LQFP64)
  • 5 V tolerant digital I/O ports.

Products/packages

Type numberNorth American Type numberOrdering code (12NC)Product statusPackagePackingMarkingChemical contentLeadfree conversion date
SAA7111AH/V4SAA7111AHBG9352 702 24557Volume productionSOT393-1
(QFP64)
Tray Dry Pack, Bakeable, MultipleStandard MarkingSAA7111AH/V4
week 21, 2004
SAA7111AHZ/V4SAA7111AHZBD9352 702 25557Volume productionSOT314-2
(LQFP64)
Tray Dry Pack, Bakeable, MultipleStandard MarkingSAA7111AHZ/V4
week 21, 2004

Pricing/ordering/availability

Type numberOrdering code(12NC)Indicative price/unit($)RegionDistributorIn stockOrder quantityInventory dateBuy onlineSamples
SAA7111AH/V49352 702 24557  NAARROW ELECTRONICS220 12/31/2008Buy onlinenot available
   NAAVNET ELECTRONICS MARKETING379 12/31/2008Buy online 
   NADIGI-KEY CORPORATION885 1/3/2009Buy online 
   NAFUTURE ELECTRONICS739 12/31/2008Buy online 
   NAMOUSER ELECTRONICS10 1/3/2009Buy online 
SAA7111AHZ/V49352 702 25557  ASIASACL - Hong Kong/Chinayes80001/05/2009Buy onlinenot available
   NAARROW ELECTRONICS561 12/31/2008Buy online 
   NAAVNET ELECTRONICS MARKETING552 12/31/2008Buy online 
   NADIGI-KEY CORPORATION983 1/3/2009Buy online 
   NAFUTURE ELECTRONICS54 12/31/2008Buy online 

Applications

  • Desktop/Notebook (PCMCIA) video
  • Multimedia
  • Digital television
  • Image processing
  • Video phone
  • Intercast.


Related applications
LCD display - discretes focus

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